OSAT and Packaging — The Post-Fab Cost Layer
Advanced packaging (CoWoS, 2.5D, 3D), why packaging has become a leading-edge bottleneck, and the OSAT competitive landscape
After a wafer leaves a fab carrying hundreds of finished die, the chips have to be packaged — separated from the wafer, mounted on substrate, connected to external pins, sealed against the environment, and tested for functionality before they ship to a device-maker. Historically this packaging step was the cheap, low-margin, low-attention layer of the chip stack — performed by OSATs (Outsourced Semiconductor Assembly and Test companies) for fabless and foundry customers, and by IDMs for their own chips. Margins were 25-30%, lower than any other layer of the stack, and the assumption was that packaging would always be the commoditized step at the back end.
That assumption broke during the AI compute cycle. Advanced packaging — specifically TSMC's CoWoS (Chip on Wafer on Substrate) 2.5D integration — became the binding constraint on Blackwell ramp through Q4 2024.
Suddenly the historically low-margin packaging layer was the bottleneck for the largest hardware capex cycle in technology history.
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What this lesson covers
- 1Why advanced packaging changed everything for AI accelerators
- 2OSAT competitive landscape and the advanced packaging opportunity
- 3Major OSAT vendors and TSMC's internal advanced packaging — capacity, scale, capability (2024)
- 4Why CoWoS capacity has been the binding constraint on Blackwell ramp
- 5ASE Technology Holding 2024 — $15B revenue, advanced packaging growth, CHIPS Act-related US positioning via Amkor partnership
- 6Where to see this on the platform
- 7Summary